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How to make layout of pad or padframe using gpdk180 (180nm tech.) in cadence virtuoso

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Apoorv1

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I am working on Cadence Virtuoso, and I am facing problem in making layout of pad and padframe of 40 pin IC. I am using gpdk180 library.
I want to make layout of an IC. And that IC will contain several circuits. I already made layouts of all those circuits. Now I want to integrate all those circuits in the form of a 40 pin IC.

I searched this on internet, and I got a tutorial of making layout of pad and padframe but he is using NCSU library. And he used pad layer, metal 3 layer and glass layer to make pad. But pad layer and glass layer is not there in gpdk180 library.

So, can you please tell which layers I have to use and what are the steps to make the layout of a pad of an IC using gpdk180 library..??
 

erikl

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Is this just an exercise, or do you need this chip to be fabricated? In the latter case you need to use a foundry PDK which usually includes a library with pad ring and I/O pads. As a student you can access such PDKs e.g. via your university from MOSIS or Europractice.

If you are doing an exercise, just add the necessary layers (in the LSW, resp. into the technology file) and use the NCSU pad library.
 

dick_freebird

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It's my experience that pad construction, like scribe, is
very foundry- (even flow-) idiosyncratic. Add to this the
differences between wirebond and bump attach and you
have enough variety that you need to go to the destination
fab, not the Distributed Fount o' Internetz Wisdom, for your
answer.

And of course gpdk has no foundry connection, right?

You could add your pad (silox, whatever) to the display
layer table and stream layer table, and fake it I suppose.
Still many low level style differences, like whether the
pad includes all metals or only top, whether the vias
between layers are standard or pad-cut-scale and
how dense, if standard, the nesting of metal layers and
any under-pad wells & guardrings, on and on.
 

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