dear respectives.."getting asic design is not an easy thing"..is the statement comes out from everyones mouth..but i am so desired in learning asic.. but i am unable to find which is first and which is last..this subject is like a sea.. please provide me a small boat so that i can observe the subject..?[/b]
first do digital design,
then code it in HDL ( verilog or VHDL),
then synthesize the design,
then insert DFT to make it testable,
then timing analysis,
then place & route,
then timing analysis with parasitic extractions,
finally tape-out for fab.
actually ASIC design consists a big flow. dont afraid. jest i have given the flow.