how to introduce clock delay inside cpld?

[catrat]

clock delay cpld

Hi, friends
To meet the Tsu requirement, I want to introduce clock delay in the cpld ( not fpga, just only cpld like max3000a, lsimach4000v), how can I do that?
Thanks!

Regards

 

[power-twq]

clock delay in cpld

I think that can't be implemented by adding a buffer outside

FPGA chip.

best regards

Hi, friends
To meet the Tsu requirement, I want to introduce clock delay in the cpld ( not fpga, just only cpld like max3000a, lsimach4000v), how can I do that?
Thanks!

Regards

 

[r_e_m_y]

delay in cpld

Hi catrat,

For @ltera device, you can to this by adding LCELL component.
in vhdl, the LCELL declaration is :

COMPONENT LCELL
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

The @ltera tool will take the LCELL component in its library.
This will introduce delay, but this delay cannot be guaranted in temperature, component date code, power consumption ... Only a maximum delay is given by @ltera

I hope this will help you.