Re: How to introduce small delay in clock path ?
Maybe I should have put
register retiminig. I'm a lazy typer. ;-)
No programmable clock trees in any FPGA vendors offering as of 2016, though there may be some niche products that never took off like Arcronix (sp?) that were a sort of asynchronous FPGA that didn't exactly have a clock network but would take advantage of skew in a clock-like (latch) path.
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As I recall and verified
Achronix (corrected spelling) did come out with a real product that abandoned the asynchronous FPGA idea and went with a more traditional FPGA architecture (LUT, FF, DSP, BRAM etc). They have extremely low % of market penetration behind Xilinx, Altera, and Microsemi (not sure where Lattice stands currently).
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Wait I just had a hideous kludge inspiration!
Run the clock you are using through a PLL and produce another version of the clock that is skewed by the needed delay and run the other register off that clock...
Oops, just realized you didn't want coding changes.
So there is a way to add useful clock skew delay, but it requires code changes, of course the OP could add this in using the FPGA editor (
I'm Joking Don't Do This It is Really Really Stupid)