[SOLVED] How to introduce a small delay in the clock path?

[UltraGreen]

How to introduce small delay in clock path ?

Hello all,

How can I add a small fixed ( known ) delay in clock path manually in fpga ?
suppose I have a setup violation and there is no hold violation , then can I add some delay in the clock path between the register to give some extra margin for fixing set up violation. I know this is not the best way to solve set up violation , but out of curiosity I want to know, how can I add fix delay in fpga in clock path without making change in rtl.

FPGA = virterx ultrascale
IDE = vivado 2015

Thanks

 

[TrickyDicky]

Re: How to introduce small delay in clock path ?

Short answer - NO
Easiest option - fix the RTL.

 

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Re: How to introduce small delay in clock path ?

Option 1.
Try running synthesis with a faster clock than the target frequency.
Increase the synthesis effort level.
Increase

​

the PnR effort to high.
Cross your fingers and hope that is enough to fix the timing problem.

Option 2
Constrain the path with a partition so all the logic in the path is near each other reducing the routing delay.

Scenario 3
If the LUT delay dominates the ttiming budget then you are out of luck and you will have to address the RTL coding problem.

 

[ThisIsNotSam]

Re: How to introduce small delay in clock path ?

Hello all,

How can I add a small fixed ( known ) delay in clock path manually in fpga ?
suppose I have a setup violation and there is no hold violation , then can I add some delay in the clock path between the register to give some extra margin for fixing set up violation. I know this is not the best way to solve set up violation , but out of curiosity I want to know, how can I add fix delay in fpga in clock path without making change in rtl.

FPGA = virterx ultrascale
IDE = vivado 2015

Thanks

unless the FPGA allows for clock skew/retiming by the USER, you can't do that. As far as I know, the devices that are currently available do not let the user mess with the clock.

 

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Re: How to introduce small delay in clock path ?

ISE 14.7 retiming option exists
Vivado - retiming has never existed, though they keep saying they plan on adding it.

 

[ThisIsNotSam]

Re: How to introduce small delay in clock path ?

ISE 14.7 retiming option exists
Vivado - retiming has never existed, though they keep saying they plan on adding it.

so let's talk about retiming because our interpretations might differ. it is quite easy to move some of the logic to after the flop to ease the timing of a setup path. this doesn't really mess with the clock tree that is implemented in the FPGA. what I am not sure the devices/tools can do is to actually delay the clock, i.e., have a programmable clock tree. I think we are not there yet although I heard some buzz about it. Essentially you want your FPGA to become closer to an ASIC and give the user/tool a new degree of freedom by letting they "stretch a path" by changing the skew in a useful manner.

 

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Re: How to introduce small delay in clock path ?

Maybe I should have put register retiminig. I'm a lazy typer. ;-)

No programmable clock trees in any FPGA vendors offering as of 2016, though there may be some niche products that never took off like Arcronix (sp?) that were a sort of asynchronous FPGA that didn't exactly have a clock network but would take advantage of skew in a clock-like (latch) path.

- - - Updated - - -

As I recall and verified Achronix (corrected spelling) did come out with a real product that abandoned the asynchronous FPGA idea and went with a more traditional FPGA architecture (LUT, FF, DSP, BRAM etc). They have extremely low % of market penetration behind Xilinx, Altera, and Microsemi (not sure where Lattice stands currently).

- - - Updated - - -

Wait I just had a hideous kludge inspiration!

Run the clock you are using through a PLL and produce another version of the clock that is skewed by the needed delay and run the other register off that clock...

Oops, just realized you didn't want coding changes.

So there is a way to add useful clock skew delay, but it requires code changes, of course the OP could add this in using the FPGA editor (I'm Joking Don't Do This It is Really Really Stupid)