Pastel
Member level 3
Hello!
I'm using Quartus with Verilog. I have made a design that works, but as it becomes bigger everyday,
I have to start splitting it into modules.
Now I have been reading books about verilog and made some experiments, but unfortunately it never
compiles, there are always errors.
What I did is as follows:
1. The working code
I made a simplified version of my code which is a lot larger, but I guess you don't want to dig in large
sources. I have an external DAC, and I'm sending data (DA) which is latched. One clk: set data, next
clk: latch data. I have also a LED blinker which divides the frequency by 50000000 to get 1Hz and blink the LED.
This first code works fine.
2. The non-working code.
See hereafter. I wanted to make a clock divider module to simplify the top module.
I have read books and also found examples. So basically all what I have to do is
to instantiate a divider with what I want to divide (clk) and set the output to the signal
I want (div_clk).
Here are my questions:
1. Can anybody tell me what's wrong?
2. I have read some conflicting stories. Some people seem to instantiate like it would
be done in C, with the variable names, but some others instantiate with expressions like
.clk_in(clk). Could anybody explain the difference?
3. Could anybody tell me how to have a color syntax when I'm posting questions?
I tried code syntax="VERILOG" but it doesn't work.
Thanks for any hint.
Pastel
I'm using Quartus with Verilog. I have made a design that works, but as it becomes bigger everyday,
I have to start splitting it into modules.
Now I have been reading books about verilog and made some experiments, but unfortunately it never
compiles, there are always errors.
What I did is as follows:
1. The working code
I made a simplified version of my code which is a lot larger, but I guess you don't want to dig in large
sources. I have an external DAC, and I'm sending data (DA) which is latched. One clk: set data, next
clk: latch data. I have also a LED blinker which divides the frequency by 50000000 to get 1Hz and blink the LED.
This first code works fine.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 module Test190801(DA, clk, dac_clk, ledb, ledr); output reg[15:0]DA; // Output to a digital analog converter input clk; // System clock (100 MHz) output reg dac_clk; // Half of system clock (50 MHz) output reg ledb, ledr; // Two leds reg[32:0] div; // One register to count clocks reg div_clk; // One very low frequency clock used to blink LED // Initialisation initial begin DA <= 0; // Set data to 0 (not crucial but cleaner) dac_clk <= 0; // Set dac clk to 1 so that the first action is load data ledb <= 1; // Illuminates blue led ledr <= 0; // Clear red led div <= 0; // Cloc divider. Set to N-1 to divide by N div_clk <= 0; // Signal that will be used to blink the red LED end // Runtime always@(posedge clk) begin // Take care of the low frequency of the LED div <= div+1; // Increment divider if(div == 49999999) begin // Reaching the 50 000 000 division to get 1 Hz for LED div <= 0; if(div_clk == 0) begin div_clk <= 1; end else begin div_clk <= 0; end end // Put the sawtooth to the DAC if(dac_clk == 1) begin DA <= DA+1; // Increment data dac_clk <= 0; // Set latch to 0 end else begin dac_clk <= 1; // Larch data to DAC end end // Take the div_clk to perform the LED blinking always@(posedge div_clk) begin if(ledr == 0) begin ledr <= 1; end else begin ledr <= 0; end end endmodule
2. The non-working code.
See hereafter. I wanted to make a clock divider module to simplify the top module.
I have read books and also found examples. So basically all what I have to do is
to instantiate a divider with what I want to divide (clk) and set the output to the signal
I want (div_clk).
Here are my questions:
1. Can anybody tell me what's wrong?
2. I have read some conflicting stories. Some people seem to instantiate like it would
be done in C, with the variable names, but some others instantiate with expressions like
.clk_in(clk). Could anybody explain the difference?
3. Could anybody tell me how to have a color syntax when I'm posting questions?
I tried code syntax="VERILOG" but it doesn't work.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 module Test190801(DA, clk, dac_clk, ledb, ledr); output reg[15:0]DA; // Output to a digital analog converter input clk; // System clock (100 MHz) output reg dac_clk; // Half of system clock (50 MHz) output reg ledb, ledr; // Two leds reg[32:0] div; // One register to count clocks reg div_clk; // One very low frequency clock used to blink LED // Initialisation initial begin DA <= 0; // Set data to 0 (not crucial but cleaner) dac_clk <= 0; // Set dac clk to 1 so that the first action is load data ledb <= 1; // Lights blue led ledr <= 0; // Clear red led div <= 0; // Cloc divider. Set to N-1 to divide by N div_clk <= 0; // Signal that will be used to blink the red LED end // Runtime Divider my_div(div_clk, clk); always@(posedge clk) begin // Put the sawtooth to the DAC if(dac_clk == 1) begin DA <= DA+1; // Increment data dac_clk <= 0; // Set latch to 0 end else begin dac_clk <= 1; // Latch data to DAC end end // Take the div_clk to perform the LED blinking always@(posedge div_clk) begin if(ledr == 0) begin ledr <= 1; end else begin ledr <= 0; end end endmodule module Divider(clk_out, clk_in); output reg clk_out; input clk_in; reg[32:0] div; initial begin clk_out <= 0; div <= 0; end always@(posedge clk_in) begin div <= div+1; if(div == 49999999) begin div <= 0; if(clk_out == 0) begin clk_out <= 1; end else begin clk_out <= 0; end end end endmodule
Thanks for any hint.
Pastel
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