How to input higher frequency using TSMC 28nm oscillator pad

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Syedaaa

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Hi,
We are using tsmc 28nm PDK. According to the documentation for the oscillator pad "PDXOEDG" we can input max upto 30 MHz with the combination of CL and ESR from the table given in PDK (attach below for reference). In our design we want to have 100 MHz as input frequency without using PLL. Can anyone help that how can we achieve this 100 MHz frequency without using PLL but the Oscillator pad or any other digital/analog IO pad. Also, if we want to use any other pad as an input clock pad rather than oscillator pad of the foundry, how can we estimate that what is the maximum allowable input frequency?



Thanks
Syeda
 

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Regular TSMC GPIO can handle close to 1GHz. You can simulate it in SPICE. No need to use the oscillator variant.
 

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Thank you for the reply, In that case which pad we should use the digital I/O or Analog I/O pad?
 

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The equation relating RC 10 to 90% to f -3dB is Tr= 0.35 /f
For RC =T to 63% of target Tr = 0.22 /f (verify)

The driver impedance of 74ALCxx is suitable with Zol=Vol/Io for low level and symmetrical for high level. This is Vdd and temperature dependent ( slower at low Vdd and hot ) But I recall @ 3.3 V Zo= 25 Ohms +/-33% to 50% but stated as Vol max @ Io for Vdd = ? @ ? 'C

Thus if you have 33 Ohms max and want 100 MHz, RC = 0.22/100MHz, C= 0.22/100M / 33R = 66 pF which is easily achieved with input capacitance and stray pF/mm.. If necessary, add terminator to long trace between clock and input. e.g. 100 pull up/down = 50 ohm.
 

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