Hi
I have designed a CMOS LC VCO.
I want to improve the output swing of the VCO.
Pre layout simulations show that the output swing is 1.4 V (0.18u process)
But after laying out all the blocks the output swing drops to 0.8V peak to peak.
I would appreciate it if someone could help me figure out how to increase the output swing. Is it because of parasitic resistance that the gain is lowered?
The ground plane in my design is in the lower most metal.. should i change it to a metal layer with lower resistivity?
are you using minimum width traces and minimum number of vias? i did an extraction with QRC the other day using minimum sized traces/vias for power/ground, and saw that vdd loses 50mV from bondpad to m1 (8 metal process).
I'm also facing a similar problem i.e. discrepency between pre & post layout simulation result of a Class C vco. The tail current jumps to twice as much. Any idea how to debug the issue?
you can check the quality factor of the coil after extraction and compare before extraction , it seems that the quality factor of the coil drops significantly after extraction ,
you can check the quality factor of the coil after extraction and compare before extraction , it seems that the quality factor of the coil drops significantly after extraction ,