how to increase phase margin

[bor]

hi everyone..
now.. i am working to improve the 741..the problem is when i try to increase the dc gain, the phase margin will drop...or not exceed 50 degree.. so what should i do?... i try to have about 121 dB for dc gain voltage.

 

[Circuit_seller]

increasing phase margin

Hi

You should decrease frequency of the dominant pole. this change decreases your unity gain BW, but increases your phase margin.

Regards

 

[raymond33]

increase phase margin

First what do you need a gain of 121 dB?
Because big gain ----> stability hard!
If your circuit have got a Miller capacitance you need to increase Miller capacitance value.

 

[sutapanaki]

how to incerase phase margin

tell me if I'm wwrong, but if I remember well from my school books 741 is internally compensated for unity gain operation and it should be stable for all feedback configurations.

 

[bor]

lm1085 gain margin

ehmm..why i want such a high gain..this is my target spec design..so at the first stage i like to increase the DC gain and as well as to maintain the stability..but it cannot..so if my gain is too high what is the reasonable value for it? thank you

 

[jiangwp]

howto increase 741 bandwidth

If you need to drive large capactor or small resistance, a buffer wtih unit gain is addtion added to the classic 741 due to the effection with load to phsae margin.

I think the topology of 741 can meet you requriement of 121dB gain.

But i want to know what the UBW of the regualted 741 is and what you process is ?

Maybe the compensation of regulator 741 is only Miller compensation. What is to be done is to place right the poles and zeros. Then the gain and BW is needed to be assigned rightly. Then the good bais current is needed to be placed.

 

[bor]

gain margi and phase margin

ehmm..ok in my design it consist of several targets, however
i like choose DC gain, bandwidth and phase margin as a champion. Here i like to achieve 121 dB, 4 hz(bandwidth) and as well as 60 degree. After i try to adjust the resistor at bias stage and capacitor, the DC gain is started to increase but the phase margin drop,

Mr. jiangwp..how to do the buffer? and also hoe to determine the right poles and zeros..as u know i am not very fimiliar with poles and zero...anyway thanks for the info guy...

 

[alok_ky]

phase margin increase

reduce loop gain......add dominant pole

 

[pillar_chen]

increasing phase margin

split the dominant pole and the second pole.

 

[mince]

phase margin too high

Increase the compensation capacitance.
Increase the current in the second stage.