How to increase FPGA performance ?

[hamadeh]

Hi guys,
Is there a manual or some key points to follow in order to increase the performance of an HDL based design.
Thanks

 

[eda_wiz]

Yes there is...You can follow the coding guidelines provided by the synthesis tool you use.

I suggest you look at book "REUSe Methodology Manaual" ..

also c this link
http://twins.ee.nctu.edu.tw/courses/ip_core_01/lab_hw_pdf/RTL_coding_guidelines.pdf

 

[hamadeh]

Ok thanks,
But isn't there a a tool or something that can give u some hints about ur code ?

 

[masai_mara]

Ok thanks,
But isn't there a a tool or something that can give u some hints about ur code ?

There are lint tools which help clean up your code, but no there are no tools to help increase the performance of the design. The synthesis tools take your input code and optimize the redundant logic but nothing more. For improving the throughput/speed of your design, you need to learn concepts such as pipelining and parallel processing.

 

[hamadeh]

For improving the throughput/speed of your design, you need to learn concepts such as pipelining and parallel processing

Thats exactly what I want to do, is there a starting manual for such a thing, or a book with good examples on this issue ?
Thanks

 

[arunragavan]

Give a good reading on Sistolic arrays!

Pipelinin is the method of speeding up the data during processing..
You cud also choose reconfigurable computing, wud reduce the time for turn around.

to my knoledge pipeling/ parallel processing s a good method to speed up the processin..

ive materials on both.. cud help u if u need those.

with regards,

 

[hamadeh]

What I would like to know is how to use the concept of pipelining and parallel processing in an effective way by HDL languages, I am familiar with the idea of pipelining from a hardware architecture prospective, so do you have any good material for that ?
Thanks

 

[buzkiller]

For Xilinx FPGA's floorplanning gives good results - typical increase of 10-20%
You may also use RPM for small critical blocks, especially if they are used in different places in your design.
Physical Synthesis tools (Amplify etc) are also effective sometime and much easier to use than Floorplanner.
Xilinx have bought PlanAhead lately, it supposebly has very good automatic physical synthesis engine

 

[Ace-X]

Xilinx have bought PlanAhead lately, it supposebly has very good automatic physical synthesis engine

They already offer it for Virtex-4 for very interesting price 15K$, so it is supposed to be very powerful physical level optimizer.

 

[bibo1978]

As has been hinted mainly pipelinning and parallel processing are the two main axis you can work at to achieve a more speed in your design,
Pipelinning in general can achieve a very high speed with a small cost in area and cost of latency, parallel processing can improve your latency but it will affect the area hardly.
In general speed and area are inversely proportional, your decision should mainly depends on the application.
It is not only pipelinning and parallel processing there is many other aspects with less effect, like floorplanning, coding style and innovation design solutions this may as well affect the design.
As with planahead I dunno if it worth the 15K$ "does it?"

 

[mkenobi]

Give a good reading on Sistolic arrays!

Pipelinin is the method of speeding up the data during processing..
You cud also choose reconfigurable computing, wud reduce the time for turn around.

to my knoledge pipeling/ parallel processing s a good method to speed up the processin..

ive materials on both.. cud help u if u need those.

with regards,

I am interested in sistolic array implementation and pipelining with vhdl. could you post some materials about this subject?

 

[arunragavan]

Dude take a look at this regarding systolic array..

am also tryin to implement a parallel architecture.. one of the best and accalimed algorithm is systolic.


with regards

 

[brmadhukar]

Hi,
For prototypes, I suggest use only 60% of the resources. It gives you better speed performance.
BRM

 

[mkenobi]

Dude take a look at this regarding systolic array..

am also tryin to implement a parallel architecture.. one of the best and accalimed algorithm is systolic.


with regards

thanks for the post. are you familiar with any lecture notes or books describing how to implement systolic arrays and pipelines using VHDL?

 

[arunragavan]

well dude.. jes take a design which is already implemented and then try to read thru it.. and u shall understand the basic implementation pattern.. take for example

SAD (sum of absolute difference) -- this follows systolic array..

h**p://ce.et.tudelft.nl/publicationfiles/734_14_fpt2002.pdf

take a look at this.. this wud surely help

with regards,

 

[keen]

Where to find the eval. PlanAhead or maybe the full version,
with the lic file ofcouse ..


br Keen

 

[phoenixfeng]

good coding style
good synthesis tool

 

[Johnson]

KEEN: it is ready to download!

 

[power-twq]

the attachment is a good reference, good luck.

Hi guys,
Is there a manual or some key points to follow in order to increase the performance of an HDL based design.
Thanks