How to include a file to use the various tasks in my testbench ?

[balasub]

verilog tasks

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hi,
i have a verilog file containing the various tasks....

How do i include this file to use the various tasks in my testbench..

this file also has tasks which are dependent on the state of a signal inside the BFM.

 

[deepu_s_s]

verilog tasks

how about 'include ? i think this works

 

[venkatesankalidass]

Re: verilog tasks

`include "full\path\name.v"
like the above example use ur design to include task

note all the task present iiside the module

 

[satishkumar]

verilog tasks

hi send some more detail data regarding task `include

 

[kelvin_sg]

verilog tasks

venkatesankalidass wrote that.

it's the exact trick in Verilog I like most.
with `include one can write 10k lines of codes in single module without tiring out scrolling ultraedit..

i dream vhdl has that too.