APR after Synthesis using Synposys DC
fine one path after some inverter(with 25 loading ) max delay is 7ns (normal is <1ns)
what command or parameter can improve this?
ARP?? do you mean APR?
some invertersome inverter << I don't understand what's that
Just a guess.. You might got into big loading problem, long wire and large fanouts. Buffer insertion and buffer tree might help you...you can fix it in dc or backend tools. What's the processing technology you are using?