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How to improve LDO high frequency PSRR (40-100MHz)?

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Junior Member level 3
Aug 19, 2009
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Hi all
I want to design LDO with PSRR >40db till 100Mhz
But I have problems
1. LDO PSRR limit by amplifier bandwidth ≈ 10-100KHz (with external capacitor)
2.Output capacitor about 2uF should help improve high freq PSRR but when I simulate with capacitor RLC model and package RLC model no PSRR improving
inductance kill all offchip capacitor influance .
All paper which relate to LDO PSRR issue don't take to account Inductance

My question is anybody meet the same question and know how I can anyway improve high freq PSRR

psrr bandwidth

I want to make this problem more clear.
1,how much bonding inductance you have added?what does your RLC model like?
2,you ask for the whole frequency band below 100MHz? can you just ask for the frequency you care about?because the PSRR detoriated from the amplifier bandwidth until it reach the output pole the capacitor bringing.

how do you model an ldo in ads

The Freq is from 0-->80MHz
and RLC model is

psrr frequency

In a PMOS LDO, the Cgd is a killer. You cannot add
enough gate (Cgs) shunt to settle down the output
device. When the supply moves and the load doesn't,
Cgd dumps charge into the gate.

Get away from small signal and look at transient
behavior. You want to see where the gate perturbation
really comes in, is it in phase or antiphase? Where is
it entering and where it is being gained up?

You may have to try compensating with an inverted
image current but this can be a nastiness all its own.

how to simulate ldo psrr

If the internal Cload is limited the high frequency PSRR is limited by


The external cap could help a little bit because the series inductance and a good quality external cap make an additional lowpass.

But the solution is LDO chaining.

If you increase the size of the LDO-PMOS by 2 you increase Cgd by 2 too. So the PSRR goes down by 6dB. But because the drop is only half you can insert a second LDO which gives total more than 6dB improvement.

ldo high bandwidth

Hi all
Thank you for replay

As I understand all your comments are for low and medium FREQ
Where LDO’s error amplifier is relevant (10K-1MHz common LDO)

In my case I want improve high freq PSRR 40-100MHz

My LDO drop voltage is about 100-200mV and I have area constrains
(by the way how two cascaded LDO can improve high freq PSRR)

Somebody already met this issue ?

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