vovan76
Junior Member level 3
Hi all
I want to design LDO with PSRR >40db till 100Mhz
But I have problems
1. LDO PSRR limit by amplifier bandwidth ≈ 10-100KHz (with external capacitor)
2.Output capacitor about 2uF should help improve high freq PSRR but when I simulate with capacitor RLC model and package RLC model no PSRR improving
inductance kill all offchip capacitor influance .
All paper which relate to LDO PSRR issue don't take to account Inductance
My question is anybody meet the same question and know how I can anyway improve high freq PSRR
Thanks
I want to design LDO with PSRR >40db till 100Mhz
But I have problems
1. LDO PSRR limit by amplifier bandwidth ≈ 10-100KHz (with external capacitor)
2.Output capacitor about 2uF should help improve high freq PSRR but when I simulate with capacitor RLC model and package RLC model no PSRR improving
inductance kill all offchip capacitor influance .
All paper which relate to LDO PSRR issue don't take to account Inductance
My question is anybody meet the same question and know how I can anyway improve high freq PSRR
Thanks