How to implimente a CDR (clock and data recovery) circuits.

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dd2001

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cdr clock

Any one know this topic? I aready know PLL, but how to apply PLL to it?
 

Basically the PLL is used to regenerate the clock from the data
stream. The clock is aligned with the center of the data patern,
so that the data can be deserialised. The data is generally scrambled
to insure there is a minimum transitions per unit of time to keep
the PLL locked.

If you do a search for SONET OC12 components you will find a lot
of doc relative to CDR.
 

I'm not sure if this is what you want.
 

sorry, a mistake!
 

and its codes!
 

Thanks both pf shell3 and vsop.

 

use multi phase clock select data

use multi phase clock , & select "right" clock to fit "setup time "
usual let "sampling clk in middle of "in_data" "
 

Re: How to implimente a CDR (clock and data recovery) circui

cdr
youcan use pll
or dll
oversample
or
*n speed clock
 

Re: How to implimente a CDR (clock and data recovery) circui

you can use pll (with a ring osc for VCO) to generate multiple clocks

with different phase (for example 0, 45, 90, 135, 180, 225, 270, 315),

then use some algorithm to select appropriate phase clock to use.




dd2001 said:
Any one know this topic? I aready know PLL, but how to apply PLL to it?
Click to expand...
 

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