Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Basically the PLL is used to regenerate the clock from the data
stream. The clock is aligned with the center of the data patern,
so that the data can be deserialised. The data is generally scrambled
to insure there is a minimum transitions per unit of time to keep
the PLL locked.
If you do a search for SONET OC12 components you will find a lot
of doc relative to CDR.