how to implement verilog code on FPGA

[bhavani403]

we have developed an DES algorithm in verilog.Now i have to implement in FPGA board.Now i have to build a module assigning a switch(north) to the input values that connects to the top module(main module).Please help us with some code.I am new to FPGA

 

[imbichie]

Which FPGA you are using..?

If its xilinx you can selects the ISE for the synthesis, if its lattice you can use the ISPlever and so on..