how to implement the delay

[shiningblue]

hi, I have a question about the delay implementation in chip design.

It's easy to implement in verilog for simulation, but how can it be implemented in real chip?

using flip-flop? how about the "delay 0" ?

 

[ahmad_abdulghany]

hi, I have a question about the delay implementation in chip design.

It's easy to implement in verilog for simulation, but how can it be implemented in real chip?

using flip-flop? how about the "delay 0" ?

Delay can be made simply by D-FF, but what do you mean by delay 0?

 

[kr_vinayak]

If you want to implement a particular value of delay, then you can use chain of inverters. You can size them properly to get a desired value of delay.

The concept of delay 0 (called delta delay) in Verilog is just for the purpose of simulation. In real world, you can't achieve 0 delay.

 

[tarkyss]

in std cell library, there are delay cells

 

[AlexWan]

Now wire also is delay.

 

[koppolu1981]

I think there will be macros available depending on the synthesis tool which would result in harware units like buffers/inverters with some specific delays.
We can make use of them..
Someone correct me if I am wrong...
Also if any one has such consruct pls post it