How to implement SW_reset in Verilog?

[popa]

hi,
need help with imlementation of SW reset in verilog?
anyone have examples for me?
thanks

 

[yx.yang]

SW_reset

software reset is usually done by a configure register of an external CPU. When CPU write 1'b1/1'b0 to that register, the hardware(exclude that CPU) will go to reset state, then finish the hardware reset.

 

[popa]

Re: SW_reset

My sw_reset is an internal configure register.
Can I wire it to the external HW_reset input as a solution?
can it cause me timing problems?

 

[it_boy]

Re: SW_reset

Are you planning to use this register (sw_reset) as a synchronous reset? If yes, then timing problems might occur depending on the delay on that line depending on the size of the FPGA, percentage of FPGA utilized and the routing for the reset path.

I suggest you to use the register bit (sw_reset) as an asyncronous reset for the remaining blocks.

 

[popa]

Re: SW_reset

my SW_reset is asynchronous.
I wired my SW_reset configure register together with the external reset through 'or' gate so when the configure register get '1' , an asychronous reset immediately occur.
can it cause me problems?

 

[khaila]

Re: SW_reset

my SW_reset is asynchronous.
I wired my SW_reset configure register together with the external reset through 'or' gate so when the configure register get '1' , an asychronous reset immediately occur.
can it cause me problems?

This is the way that I am using SW_RST. In addtion:
1. I sample the OR output gate to same clock domain.
2. as a global reset is synchronized; it will be traeted in the process as asynchrnous one to insure that evently reset can NOT affect FF at S/H time window.
3. limiting the the reset FF fot fixex MAX_FANOUT for synthesizes duplication.

 

[popa]

Re: SW_reset

thanks for the help.