how to implement Look-Up table in verilog

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ravi_meghadri

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Hi!

Anybody could help in writing a synthesizable verilog code for look-up table implementation. I need to design Huffman encoder with standard tables.
 

Modify this code sliplet and you have a look up table.


function [3:0] bit_sel;
input [63:0] hist;
input [3:0] idx;
reg [3:0] state;
begin
case (idx)
4'hF: bit_sel = hist[ 3:0 ];
4'hE: bit_sel = hist[ 7:4 ];
4'hD: bit_sel = hist[11:8 ];
4'hC: bit_sel = hist[15:12];
4'hB: bit_sel = hist[19:16];
4'hA: bit_sel = hist[23:20];
4'h9: bit_sel = hist[27:24];
4'h8: bit_sel = hist[31:28];
4'h7: bit_sel = hist[35:32];
4'h6: bit_sel = hist[39:36];
4'h5: bit_sel = hist[43:40];
4'h4: bit_sel = hist[47:44];
4'h3: bit_sel = hist[51:48];
4'h2: bit_sel = hist[55:52];
4'h1: bit_sel = hist[59:56];
4'h0: bit_sel = hist[63:60];
endcase
end
endfunction
 

what are the various ways to initialise the look-up table?
 

ravi_meghadri said:
what are the various ways to initialise the look-up table?
Click to expand...

Will this work?

wire [63:0] hist;
assign hist = 64'h0000_0000_0000_0000;
 


{64 {1'b0}}
 

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