Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to implement floating point numbers in vhdl

Status
Not open for further replies.
A

Anwesa Roy

Member level 2
Joined
Feb 24, 2014
Messages
49
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
532
We have computed the code considering integers. We need to replace the integers by float. Please help.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lms2 is
    Port (wr9,wi9,xr,xi,u : in STD_LOGIC_VECTOR (12 downto 0);
           --u : in integer;
         
           yr,yi,er,ei,wr8,wi8,zzz,sum1 : out STD_LOGIC_VECTOR (12 downto 0));
end lms2;
 
architecture Behavioral of lms2 is
 
 
--variable r,s : real range 0.0 to 15.0;
 
begin
 
process(wr9,wi9,u,xr,xi)--process also runs without the parameters,but it gives problems during simulation
--process(u,xr,xi)
variable wr : std_logic_vector(12 downto 0);
variable wi : std_logic_vector(12 downto 0);
 
--variable wr : std_logic_vector(4 downto 0) :="00010";
--variable wi : std_logic_vector(4 downto 0) :="00011";
--variable wr : std_logic_vector(4 downto 0) :=wr9;
--variable wi : std_logic_vector(4 downto 0) :=wi9;
variable yr1 : integer;
variable yi1 : integer;
variable er1 : integer;
variable ei1 : integer;
variable wr1 : integer;
variable wi1 : integer;
variable uu  : integer;
variable zz  : integer;
variable sum : integer:= 0;
begin
 
 
 
--process(xr,xi,u)
--bi <= to_integer(unsigned(k)) ;
--bj <= to_integer(unsigned(l)) ;
--bk <= bi*bj;
 
uu := to_integer(unsigned(u)) ;
wr := wr9;
wi := wi9;
 
for z in 0 to 1 loop
 
yr1 := to_integer(unsigned(wr))*to_integer(unsigned(xr))- to_integer(unsigned(wi))*to_integer(unsigned(xi));
yi1 := to_integer(unsigned(wr))*to_integer(unsigned(xi))+to_integer(unsigned(wi))*to_integer(unsigned(xr));
 
er1 := to_integer(unsigned(wr))*to_integer(unsigned(xr))-to_integer(unsigned(wi))*to_integer(unsigned(xi))-to_integer(unsigned(xr));
ei1 := to_integer(unsigned(wr))*to_integer(unsigned(xi))+to_integer(unsigned(wi))*to_integer(unsigned(xr))-to_integer(unsigned(xi));
 
wr1 :=uu*(to_integer(unsigned(xr))*to_integer(unsigned(wr))*to_integer(unsigned(xr))-to_integer(unsigned(xr))*to_integer(unsigned(wi))*to_integer(unsigned(xi))-to_integer(unsigned(xr))*to_integer(unsigned(xr))-to_integer(unsigned(xi))*to_integer(unsigned(wr))*to_integer(unsigned(xi))-to_integer(unsigned(xi))*to_integer(unsigned(wi))*to_integer(unsigned(xr))+to_integer(unsigned(xi))*to_integer(unsigned(xi))+to_integer(unsigned(wr)));
wi1 :=uu*(to_integer(unsigned(xr))*to_integer(unsigned(wr))*to_integer(unsigned(xi))+to_integer(unsigned(xr))*to_integer(unsigned(wi))*to_integer(unsigned(xr))-to_integer(unsigned(xr))*to_integer(unsigned(xi))+to_integer(unsigned(xi))*to_integer(unsigned(wr))*to_integer(unsigned(xr))-to_integer(unsigned(xi))*to_integer(unsigned(wi))*to_integer(unsigned(xi))-to_integer(unsigned(xi))*to_integer(unsigned(xr))+to_integer(unsigned(wi)));
 
 
--o <= std_logic_vector(to_unsigned(i,5));
wr := std_logic_vector(to_unsigned(wr1,13));
wi := std_logic_vector(to_unsigned(wi1,13));
 
zz :=z;
sum := sum+2;
 
 
 
yr <= std_logic_vector(to_unsigned(yr1,13));
yi <= std_logic_vector(to_unsigned(yi1,13));
 
er <= std_logic_vector(to_unsigned(er1,13));
ei <= std_logic_vector(to_unsigned(ei1,13));
 
wr8 <= wr;
wi8 <= wi;
 
zzz <= std_logic_vector(to_unsigned(zz,13));
sum1 <= std_logic_vector(to_unsigned(sum,13));
 
end loop;
 
end process;
 
 
end Behavioral;
 
Last edited by a moderator:

Look into the VHDL floating point package. It's part of the 2008 revision to the standard.

Kevin
 
Present implementations of ieee.float_pkg are only formally synthesizable but don't produce useful code due to lack of pipelining. You better refer to float IP provided by FPGA vendors like Altera, Xilinx etc. Floating point arithmetic consumes considerable FPGA resources, in most cases you better use fixed point implementations.

It's not clear to me if the problem actually targets on FPGA synthesis or is more a kind of VHDL syntax exercise to be used in a simulator? In the latter case, real type may be used.
 
FvM said:
Present implementations of ieee.float_pkg are only formally synthesizable but don't produce useful code due to lack of pipelining. You better refer to float IP provided by FPGA vendors like Altera, Xilinx etc. Floating point arithmetic consumes considerable FPGA resources, in most cases you better use fixed point implementations.

It's not clear to me if the problem actually targets on FPGA synthesis or is more a kind of VHDL syntax exercise to be used in a simulator? In the latter case, real type may be used.
Click to expand...

Sir could you please show us a program that shows addition and multiplication of real signals/variables in vhdl?
 

K-J said:
Look into the VHDL floating point package. It's part of the 2008 revision to the standard.

Kevin
Click to expand...

Sir could you please show us a vhdl program which shows addition and multiplication of floating point numbers
 

Anwesa Roy said:
Sir could you please show us a program that shows addition and multiplication of real signals/variables in vhdl?
Click to expand...

Anwesa Roy said:
Sir could you please show us a vhdl program which shows addition and multiplication of floating point numbers
Click to expand...

In both cases it is:
Code VHDL - [expand]
1
2

c <= a * b;
c <= a + b;


You should read up on how VHDL allows overloading. Use the correct package and multiplication or addition is defined for that type, i.e. float type use the floating point package, fixed use the fixed point package, unsigned use the numeric standard pacakge, etc.
 

ads-ee said:
In both cases it is:
Code VHDL - [expand]
1
2

c <= a * b;
c <= a + b;


You should read up on how VHDL allows overloading. Use the correct package and multiplication or addition is defined for that type, i.e. float type use the floating point package, fixed use the fixed point package, unsigned use the numeric standard pacakge, etc.
Click to expand...


Sir,
It would be highly helpful if you post the entire code starting from the libraries to be added, to real type declarations, to the addition and multiplication code.
 

here is the full code. No libraries are needed as real type is part of std.standard, which is imported by default into each VHDL design

Code: 
entity real_maths is
  port (
    a, b : in real;
    c, d, e, f : out real
  )
end entity real_maths;

architecture this_will_not_synthesise_because_real_type_is_not_synthesisable of real_maths is
begin
  c <= a + b;
  d <= a - b;
  e <= a * b;
  f <= a / b;
end architecture this_will_not_synthesise_because_real_type_is_not_synthesisable;
 
TrickyDicky said:
here is the full code. No libraries are needed as real type is part of std.standard, which is imported by default into each VHDL design

Code: 
entity real_maths is
  port (
    a, b : in real;
    c, d, e, f : out real
  )
end entity real_maths;

architecture this_will_not_synthesise_because_real_type_is_not_synthesisable of real_maths is
begin
  c <= a + b;
  d <= a - b;
  e <= a * b;
  f <= a / b;
end architecture this_will_not_synthesise_because_real_type_is_not_synthesisable;
Click to expand...

Sir what do you mean by code is not synthesizable?
 

Anwesa Roy said:
Sir what do you mean by code is not synthesizable?
Click to expand...
It can't be converted to logic, the code can be run in simulation but can't be implemented (compiled - synthesis/elaboration) into logic that can be downloaded into FPGA hardware.
 
Sir we have run the following program but it shows the following error: non-constant real-valued expression is not supported

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test3 is
    Port ( a, b : in real;
   c, d, g, f : out real);
end test3;

architecture Behavioral of test3 is

begin

  c <= a + b;
  d <= a - b;
  g <= a * b;
  f <= a / b;

end Behavioral;
 

it shows the following error: non-constant real-valued expression is not supported
Click to expand...
Confirms the previous comment by ads-ee. Real arithmetic code can't be compiled in a FPGA synthesis tool, only in a simulation tool.

If you are intending synthesizable code to be implemented in a FPGA, don't use real for variables and signals.
 

FvM said:
Confirms the previous comment by ads-ee. Real arithmetic code can't be compiled in a FPGA synthesis tool, only in a simulation tool.

If you are intending synthesizable code to be implemented in a FPGA, don't use real for variables and signals.
Click to expand...

What simulation tool should we use. We are using vivado 2014.4
 

Anwesa Roy said:
What simulation tool should we use. We are using vivado 2014.4
Click to expand...
What is your end goal? Simulation only or implementing it in real hardware?
- If simulation only: Use type real and a simulator like Modelsim or Aldec
- If implementing it in real hardware: Use VHDL-2008 floating point package but don't expect high clock cycle performance.
- If implementing it in real hardware and you want high clock cycle performance: Use vendor supplied IP. Based on your posts so far, I would expect you to have a lot of difficulty getting this to work since you have shown little motivation to do your own work.

Kevin Jennings
 

K-J said:
What is your end goal? Simulation only or implementing it in real hardware?
- If simulation only: Use type real and a simulator like Modelsim or Aldec
- If implementing it in real hardware: Use VHDL-2008 floating point package but don't expect high clock cycle performance.
- If implementing it in real hardware and you want high clock cycle performance: Use vendor supplied IP. Based on your posts so far, I would expect you to have a lot of difficulty getting this to work since you have shown little motivation to do your own work.

Kevin Jennings
Click to expand...

For now we just want to simulate the program...later we might consider implementing it using hardware/fpga.
 
Last edited:

Anwesa Roy said:
For now we just want to simulate the program...later we might consider implementing it using hardware/fpga.
Click to expand...
Those words alone say to me: I think like a software programmer not a hardware engineer.

After looking at your "program" in post #1, that makes extensive use of variables, I must be correct in my assumption.

That "code" is written like software, it looks like something you would write in an imperative programming language and not something that represents hardware, which is what VHDL (VHSIC Hardware Description Language) is primarily used for. Writing VHDL like this will never synthesize to something reasonably useful (if it synthesizes).

Try thinking in terms of pipelined operations and breaking the design up into sequential operations that are controlled by "states" (i.e. counters, FSM, etc). This hardware approach will allow for a design that is synthesizable and will run at a reasonable and useful clock frequency.
 

non constant real valued expression is not supported

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lms2 is
    Port (wr9,wi9,xr,xi : in STD_LOGIC_VECTOR (12 downto 0);
           --u : in integer;
         
           yr,yi,er,ei,wr8,wi8,zzz,sum1 : out STD_LOGIC_VECTOR (12 downto 0));
end lms2;

architecture Behavioral of lms2 is
signal a,b :real;
--signal yr11, yi11 : real;

--variable r,s : real range 0.0 to 15.0;

begin

process(wr9,wi9,xr,xi)--process also runs without the parameters,but it gives problems during simulation
--process(u,xr,xi)
variable wr : std_logic_vector(12 downto 0);
variable wi : std_logic_vector(12 downto 0);

--variable wr : std_logic_vector(4 downto 0) :="00010";
--variable wi : std_logic_vector(4 downto 0) :="00011";
--variable wr : std_logic_vector(4 downto 0) :=wr9;
--variable wi : std_logic_vector(4 downto 0) :=wi9;
variable xr1 : real :=3.2;
variable xi1 : real :=4.1;
variable dr1 : real :=5.2;
variable di1 : real :=4.4;
variable yr1 : real;
variable yi1 : real;
variable er1 : real;
variable ei1 : real;
variable wr1 : real := 1.8;
variable wi1 : real := 2.1;
variable u   : real :=0.2;


variable f : real := 3.2;
variable g : real := 2.6;
variable h : real;
variable hh : real;

begin

h := f+g;
hh := f*g;
a <= h;
b <=hh;

--process(xr,xi,u)
--bi <= to_integer(unsigned(k)) ;
--bj <= to_integer(unsigned(l)) ;
--bk <= bi*bj;





for z in 0 to 3 loop

yr1 := wr1*xr1-wi1*xi1;--line1
yi1 := wr1*xi1+wi1*xr1;--line2

er1 := (wr1*xr1)-(wi1*xi1)-dr1;--line3
ei1 := (wr1*xi1)+(wi1*xr1)-di1;--line4

wr1 := u*(xr1*er1-xi1*ei1)+wr1;--line5
wi1 := u*(xr1*ei1+xi1*er1)+wi1;--line6



end loop;

--yr11 <= yr1;
--yi11 <= yi1;

end process;


end Behavioral;

We are implementing LMS algorithm . If we are adding line 5 and line 6 (as indicated by comments), we are getting error right from line 1 (as indicated by comments) that "non constant real valued expression not supported". However when we are omitting line 5 and line 6, we are not getting the error. Please ignore the STD_LOGIC_VECTORS(in and out)added in the beginning, as they are reserved for future use.
 

Re: non constant real valued expression is not supported

You cannot use the real type for synthesis, other than for constants.
You code is full of real variables - they are not supported.
 

Re: non constant real valued expression is not supported

TrickyDicky said:
You cannot use the real type for synthesis, other than for constants.
You code is full of real variables - they are not supported.
Click to expand...

Sir,we dont need a synthesisable code, for now we just need it for simulation. the code ran for line1,2,3,4, and also computed the results h := f+g; hh := f*g; which are stored in signal a and b(this is right after begin inside process). We saw the values in simulation and it gave the correct results for signals a and b. However we are getting error on adding line 5 and 6.
 
Last edited:

Re: non constant real valued expression is not supported

The error you supply is a synthesis error. Your code will have no problems in simulation.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top