Can any one send me How to implement AND,OR,NOT ,XOR and NAND gates with time table?
Can anyone send me the good material for fundamentals from flip flops to state machines?
I didn't get you.I need to implement OR gate using 2:1 mux.
For example A and B are 2 inputs and y is the output.
To implement OR gate using mux i need to connect one of the input to selection
line (0).Then if B is connected to selection line the o/p of mux be A.
Is it correct?
To implement an OR gate with inputs 'x and y' and with output 'z'. join select input of mux with 'x',input 1 with 'vdd', input 0 with 'y' and output with 'z'.