How to implement a Mealy state machine in VHDL?

[ZeroCool666]

hello everyone,
could someone please tell me how to implement a mealy state machine in VHDL, i need a structural description. Or if someone already has one implemented could you tell me the output for these sequence: 01101100?
Thank you

 

[amraldo]

Re: Mealy state machine

The output depends on your state machine behavior.
What's the HDL language you are using.
--
Amr

 

[ZeroCool666]

Re: Mealy state machine

I am using VHDL, working in Active HDL version 6.3 if thats any help
well then if u could help me code a mealy state machine and then I think I can manage
Thank you

 

[amraldo]

Re: Mealy state machine

Thats an explanation of what is a mealy state machine @ https://en.wikipedia.org/wiki/Mealy_machine
There s a VHDL example @ https://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
just search for Example of a Mealy Machine
--
Amr

 

[ZeroCool666]

Re: Mealy state machine

thank you very much...that was really helpfull