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How to implement a Mealy state machine in VHDL?

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ZeroCool666

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hello everyone,
could someone please tell me how to implement a mealy state machine in VHDL, i need a structural description. Or if someone already has one implemented could you tell me the output for these sequence: 01101100?
Thank you
 

amraldo

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Re: Mealy state machine

The output depends on your state machine behavior.
What's the HDL language you are using.
--
Amr
 

ZeroCool666

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Re: Mealy state machine

I am using VHDL, working in Active HDL version 6.3 if thats any help
well then if u could help me code a mealy state machine and then I think I can manage
Thank you
 

ZeroCool666

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Re: Mealy state machine

thank you very much...that was really helpfull:D
 

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