ZeroCool666
Newbie level 3
hello everyone,
could someone please tell me how to implement a mealy state machine in VHDL, i need a structural description. Or if someone already has one implemented could you tell me the output for these sequence: 01101100?
Thank you
could someone please tell me how to implement a mealy state machine in VHDL, i need a structural description. Or if someone already has one implemented could you tell me the output for these sequence: 01101100?
Thank you