hello everyone,
could someone please tell me how to implement a mealy state machine in VHDL, i need a structural description. Or if someone already has one implemented could you tell me the output for these sequence: 01101100?
Thank you
I am using VHDL, working in Active HDL version 6.3 if thats any help
well then if u could help me code a mealy state machine and then I think I can manage
Thank you