How to implement a 2x clock multiplier in digital logic?

[zhiling0229]

Hi,

Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz?

Thanks

 

[tom_hanks]

digital clock multiplier

chk xilinx application note...
they have lots of note...
to achiecve a multiplier using a counter

 

[VVV]

clock multiplier

The obvious answer is to use a PLL. You can try the good old 4046, or the newer 74hc4046. https://www.onsemi.com/pub/Collateral/MC74HC4046A-D.PDF

But you can also use for example two one-shots (choose the timeout carefully), one treiggered on the rising edge, the other on the falling edge of the input signal. By OR-ing the outputs you obtain twice the input frequency. The duty-cycle will not be exactly 50%, nor very stable, though.

 

[zhiling0229]

clock multiplier logic

I'm sorry but i still could not see how this can be implemented using basic logic gates or with a flip flop.

Can anyone help me to illustrate the digital logic schematic for the clock multiplier?

 

[VVV]

18:35 clock

This is what I meant: the red wave is the input. The blue wave is the output of the first one-shot, triggered on the rising edge. The green wave is generated by another one-shot, triggered on the falling edge. The yellow is the OR between the green and the blue waves.

Of course, you can use the same one-shot for both jobs, but you have to make it trigger on both edges. There are parts out there that already do that, I think. It saves you the OR gate.

Instead of one-shots you could use a few gates in series, to just get some delay. The pulses duration would be much shorter, but still, the output frequency would be correct, i.e. twice the input frequency.
Now you can understand why the output duty-cucle is not going to be 50%, and why it is not going to be stable.

 

[Jepeto]

clock multiplier xilinx

Xlinix application note

 

[fazan83]

gate flip-flop clock multiplier

Xlinix application note

How to control this? I simulate it and resulting asyncronous signal.

Please advise.

Regards,
Fakhzan

 

[echo47]

clocked logic multiplier

Hi fazan83, Which simulator are you using? The Xilinx app note circuit uses the propagation delays of the D-flop and gates to generate the output pulses, so your simulation needs to include those delays.

 

[fazan83]

clock multiplier xor

Hi fazan83, Which simulator are you using? The Xilinx app note circuit uses the propagation delays of the D-flop and gates to generate the output pulses, so your simulation needs to include those delays.

Understand basically the delay of the Flip FLop is one clock cycle right?
If I am wrong then please correct me.

I am using the Tina Pro demo version.

I already tried to include those delays but the the result still the same.
Attached herewith is the sreenshot of my simulation.

Maybe there is something wrong with my simulation.
If you guys have any input on this please advise.

Thanks for your time.

 

[lordsathish]

clock multiply using gates

Is there any other means to multiply the clock to the required frequency...

 

[echo47]

clock multiplier circuits

Hi fazan83, I just now noticed your reply. Sorry for the long delay.

Your Simulation.GIF schematic shows an SN74100 (a gated latch) instead of an edge-triggered D-type flip-flop. Try an SN7474 instead.

 

[fazan83]

clock multiplier schematic

Hi fazan83, I just now noticed your reply. Sorry for the long delay.

Your Simulation.GIF schematic shows an SN74100 (a gated latch) instead of an edge-triggered D-type flip-flop. Try an SN7474 instead.

Got it. Thanks very much for your time and advise on this.

Regards,
fazan83

 

[funster]

clock multiplier circuit xilinxs application

you can delay the clock by some time, then XOR the delayed clock with the

origional one, the output frequency will be doubled.

best regards

Hi,

Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz?

Thanks

 

[ryusgnal]

clock multiplier using gates

Hi fazan83, I just now noticed your reply. Sorry for the long delay.

Your Simulation.GIF schematic shows an SN74100 (a gated latch) instead of an edge-triggered D-type flip-flop. Try an SN7474 instead.

Got it. Thanks very much for your time and advise on this.

Regards,
fazan83

Can you show the screenshot?

 

[echo47]

ckt of freqency multiplier using 566

Scroll up a few messages to find fazan83's Simulation.GIF screenshot.

 

[ryusgnal]

onsemi clock multiplier schematic

Scroll up a few messages to find fazan83's Simulation.GIF screenshot.

Yes but its looks like the clock multiplier is not working. Fout ≠ 2×Fin

 

[echo47]

d flip flop clock multiplier

Oops, I misunderstood your screenshot request. Simulation.GIF is a screenshot of the bad behavior, before changing the SN74100 to an SN7474.

If you wish to see a snapshot of the good behavior with the SN7474, then maybe you can ask fazan83 directly. He may not be watching this discussion anymore.

 

[ojasvita]

logic multiplier

Yeah u can multiply the Frequencies but the code wont be synthesizable.
None the less u can implement it in the testbench