how to identify the no.of clock cycles during simulation of design?

[anusha vasanta]

Hi all,
i had a very basic doubt as per the design i can understand the no.of clk cycles, but during my simulation how can i identify simply the no.of clock cycles my design is taking. any easy way help me
thanx in advance..

 

[sharath666]

You will have to count. Else by knowing the clock period and time between input and output, you can determine it(Output-Input)/clock period...

 

[TrickyDicky]

Put a counter in the testbench...

 

[shaiko]

With VHDL ( assuming you meant positive clock edges )

signal counter : natural := 0 ;

process ( clock ) is
begin
  if rising_edge ( clock ) then
     counter <= counter  + 1 ;
  end if ;
end process ;

 

[dpaul]

Hi,
In my opinion the approach to follow depends on your design complexity. I presume you can view your simulation via waveforms.
1> For simple designs look at the CLK signal when the simulation ends. Note the time indicated by the cursor for the CLK signal. Divide this time by 1 CLK period to get the no. of clk cycles. Sarath666 already mentioned this.
2> The other is the counter method (shaiko's post). Make the counter to stop counting by checking if a particular signal is asserted or de-asserted (this signal should be significant in determining if your simu is over) and the counter value will give you the no. of clk cycles.