This can really depend what stage of the design you're at. If you already have a board, you know what clocks are available, or if you can generate other clocks with a DCM/PLL. You should usually what the data rate is required, so it's easy to work out what clocks are required as you should already know what busses or interfaces there are (or if you dont, that should be the first stage) and you work backwards from there. Latency should never be an issue, unless you're doing some real time image processing or something.
So you know what the data rate in and out will be, you know what your internal clock is, so now you just build the design. You can work out the latency from RTL simulation. THen you compile it, run the timing analysis, and if it meets timing, put your design straight on the board, without using the slow and laborious timing simulations (unless you're doing ASIC, then it may be important). The only reason you will need timing simulation is if you have some asynchrnous logic somewhere, but you should avoid this at all costs.