How to handle "Range must be bounded by constant expressions" error in Verilog or ?

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kbkdec15

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How to handle "Range must be bounded by constant expressions" error in Verilog/SV??

i have gone through various forms and articles . i am not getting proper solution . please help me ?
 

Re: How to handle "Range must be bounded by constant expressions" error in Verilog o

You missed to post the problem.
 

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