Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to handle "Range must be bounded by constant expressions" error in Verilog or ?

Status
Not open for further replies.
K

kbkdec15

Junior Member level 1
Junior Member level 1
Joined
May 27, 2013
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,397
How to handle "Range must be bounded by constant expressions" error in Verilog/SV??

i have gone through various forms and articles . i am not getting proper solution . please help me ?
 

Re: How to handle "Range must be bounded by constant expressions" error in Verilog o

You missed to post the problem.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top