How to halt simulation process automatically in VHDL

`timescale 1ns/100ps
 module top
(
   input  wire         pulse_in
  ,input  wire         reset_n       // active low reset
  ,output wire         pulse_out
);

  reg  [03:00] count, count_2;
  reg          out_pulse;

 // positive edge trigger counter
  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          count <= {4{1'b0}};
        end
      else
        begin
          if (count == 4'h9)
            count <= {4{1'b0}};
          else
            count <= count + 1'b1;
        end
    end

  // negative edge trigger counter
  always @ (negedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          count_2 <= {4{1'b0}};
        end
      else
        begin
          if (count_2 == 4'h9)
            count_2 <= {4{1'b0}};
          else
            count_2 <= count_2 + 1'b1;
        end
    end

  always @ (posedge pulse_in or negedge reset_n)
    begin
      if (~reset_n)
        begin
          out_pulse <= 1'b0;
        end
      else
        begin
          if (count == 4'h9)
            out_pulse <= 1'b1;
          else
            out_pulse <= 1'b0;
        end
    end

// assign pulse_out = out_pulse;
assign pulse_out = (((count == 4'h0) && (count_2 == 4'h0))? 1'b1 : 1'b0 );

endmodule

`timescale 1ns/100ps

module top_tb();

  reg          clock, reset_n;
  wire         pulse_out;
  top top_instance
    (
      .pulse_in  ( clock     ), // input 
      .reset_n   ( reset_n   ), // input
      .pulse_out ( pulse_out )  // output
    );

  initial
    begin
      clock = 1'b0;
      reset_n = 1'b1;
    #15
      reset_n = 1'b0;
    #15
      reset_n = 1'b1;
    #1000
      $stop;
    end

  always 
    begin
      #5 clock = !clock;
    end
endmodule