bhrugurajsinh
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I have a small verilog design and I am able to synthesize it and generate the gate level netlist for input to prime time.
Along with it I have the .SPEF file and .vcd file.
Currently I am able to get the power analysis reports for each subunit within the top level unit using Prime Time PX.
But now I want to get the power report for every flop within the subunit.
How can I generate that information?
Thanks in advance..!!
Along with it I have the .SPEF file and .vcd file.
Currently I am able to get the power analysis reports for each subunit within the top level unit using Prime Time PX.
But now I want to get the power report for every flop within the subunit.
How can I generate that information?
Thanks in advance..!!