bigdog
Junior Member level 2
Hello,
I want to compile my design to gate-level with DC, but I always got some cells like **SEQGEN** in the netlist, I have no idea about the reason, that seems like I didn't finish the compiling, is the anyone knows that?
Regrads,
I want to compile my design to gate-level with DC, but I always got some cells like **SEQGEN** in the netlist, I have no idea about the reason, that seems like I didn't finish the compiling, is the anyone knows that?
Regrads,