Hi,
I've read a topic about vdd/2 bias generator.But in my case I need a bias voltage follows the vdd/2,even if vdd fluctuates.
I am considering resistor divider,but the matching and area of resistors seem painful.
What about doide connected N/P mos divider?Is there anything to concern?
You could use only MOS devices will isolated bulk connection. For most processes this is only a PMOS connected as diode. The NMOS will have a strong substrate effect violating the equal voltage principle. Isolated NMOS also work but require an double WELL process.
You should consider that iff VDD is varying over time the frequency response from VDD to VDD/2 is not flat. Then you should have equal load capacitance to VDD and VSS from VDD/2.
Diode connected transistors give in general worse matching than resistors, as it is the delta(Vgs) which determines the accuracy of the output voltage.
If a small current is allowed, placing two diode-connected PMOS in series needs very big transistors lengths.
I think that reisistors give better matching for a given area constraint.
I was talking "in general".... Always it would be process dependent so it might be a good starting point... to define which kind of process are we talking about and, from there, the best answer will arise...