v_c said:First, take the 50% duty signal and delay it (using just propagation delay of gates or using RC circuit). Then take the 50% duty signal and the delayed signal and put them in an AND gate. The result should be a pulse with a duty cycle of < 50%. The trick is to pick the correct R and C values to give you the right delay. This depends on what the frequency of your duty cycle clock is. You should make the resistor a potentiometer so you can fine tune it.
Now, what I am describing above is a very rough open-loop solution. How precise does the 30% need to be?
and you dont mentioned frequency range, and if it is fixed or variable!"My key requirement is don't increase the clock jitter too much."