# How to get 1/3 duty cycle from a 50% duty cycle clock?

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#### Alles Gute

##### Full Member level 2
50 duty divide 1/3

How to get a 1/3 duty cycle clock from a 50% duty cycle clock?

#### v_c

how cd4059 program

First, take the 50% duty signal and delay it (using just propagation delay of gates or using RC circuit). Then take the 50% duty signal and the delayed signal and put them in an AND gate. The result should be a pulse with a duty cycle of < 50%. The trick is to pick the correct R and C values to give you the right delay. This depends on what the frequency of your duty cycle clock is. You should make the resistor a potentiometer so you can fine tune it.

Now, what I am describing above is a very rough open-loop solution. How precise does the 30% need to be?

Best regards,
v_c

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#### VSMVDD

##### Banned
use a CD4059 or 74HCT4059 then you can program precise division

to exact mark space needed

even by using a micro on its jam inputs

i think above method is too rought

#### pthoppay

##### Member level 4
If you want to implement in IC then use buffer as delay elements, where by sizing you control your delay.

Prakash.

#### v_c

VSMVDD -- I agree with you. As I said, mine is a very rough solution that I have used in the past when I did not have all the parts for a proper design. It is a "quick and dirty" solution.

Best regards,
v_c

#### Alles Gute

##### Full Member level 2
v_c said:
First, take the 50% duty signal and delay it (using just propagation delay of gates or using RC circuit). Then take the 50% duty signal and the delayed signal and put them in an AND gate. The result should be a pulse with a duty cycle of < 50%. The trick is to pick the correct R and C values to give you the right delay. This depends on what the frequency of your duty cycle clock is. You should make the resistor a potentiometer so you can fine tune it.

Now, what I am describing above is a very rough open-loop solution. How precise does the 30% need to be?

Best regards,
$v_C$

"use a CD4059 or 74HCT4059 " you mean use frequency divider? Like using a divider-by-3 frequency divider? Yes,in this way we can get 1/3 duty cycle clock but at 3-times lower frequency.
My key requirement is don't increase the clock jitter too much.

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#### artem

it is not possible to get 1/3 without passives or some sort of pll or duty measurement. Because it is not possible to manage rise or fall time without processing of full signal period. Of course you can design a delay circuit . It is matter of things which deserves those efforts .

But you can get 1/3 duty for twice lower frequency than your input frequency :
extract input signal's raise and fall by delay circuit (means you double the frequency , duty is not important at this time), and supply doubled frequency to synchronous counter. Then connect counter's div/2 and div/4 outputs to AND . At the AND's output you will get required duty without jitter. I dont remember chip ids but it is easy to locate them .

Counter must be synchronous, otherwise it is possible to get unwanted spikes at AND output.

#### VSMVDD

##### Banned
/n will divide the input frequency / ratio

by factors of n
so it is easily possible just using a /n

a pll is a /n counter anyway as is a 4059 that can also be used as part of the pll

so your right and so am i
however passive elements arent needed to divide a 50 % duty to get to the needed mark space

and this output of a 4059 will be incredibly stable and full adjustable in 1 % or better steps

so it wont alter the frequency
just the mark to space

attached is the plans i found online for a water fuel based gas generator

i reworked it and used the circuit as an electroplating unit
it works very well at this job
indeed

youll see both methods are employed using a 555 timer to get both frequency and pwm outputs for a dual output waveform
the base freq runs low @ 100hz - 10 khz the upper pwm output is programmable fully using a 4059

although for your job you need

using the 555 on its own is enought

www.labcenter.co.uk
or it will also open in the lite version
from v6.6 sp3 onwards

### Alles Gute

Points: 2

#### Davood Amerion

Alles Gute;
you said:
"My key requirement is don't increase the clock jitter too much."
and you dont mentioned frequency range, and if it is fixed or variable!
anyway;
if output frequency is variable only way is using PLL (and use of divide by 3 divider).

which one is most important? jitterfree or 1/3division accuracy?
if timming accuracy is most important you can use PLL
else if you want jitter free output, you can use passive methode.
also, for high frequency you can use few inverter buffer for generating needed delay.

Regards,
Davood.

#### Alles Gute

##### Full Member level 2
Thank you all for the reply. For my task, low jitter is my priority, it doesn't need a very accurate 1/3 duty cycle, a roughly 1/3 is enough. The frequency can be variable. So I guess use a divider-by-3 frequency divider is the simplest way. (although, it will cost more power since 3-times higher frequency is used.)

#### VVV

Use a divide by 3 and you get 1/3 DC, starting from a frequency three times as high. A single FF package is enough.
Take a look at this circuit.

#### montage2000

##### Member level 1
directly get it is difficult, because getting perfect delay is not a easy thing, other way may through PLL or DLL

#### cretu

##### Full Member level 2
it might help to do everything differential and CML. you will get a lower jitter

and get 5 times?

#### asic_ant

##### Banned
I've got some materials for you

##### Junior Member level 3
Hey I want to generate a programmable duty cycle from 50% duty cycle signal. But my signal is in the order of 2-50Hz. Since I want to do this on an ASIC, I think i can use an produce a programmable delay and AND the original signal with the output of the programmable delay....but how to create a programmable delay with providing delay in the order of milliseconds? Any easy circuits, coz I am a newbie...any papers that i can refer to???

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