how to genetate timing and synthesis models of hard macro

[tybhs]

I am reading a book about soc. And I dont know how to genetate timing and synthesis models ( of hard IP core) for synthesis when you want to produce a hard macro. Perhaps it is generated by an EDA tool or other method? Can tell me something about it? thanks a lot!

 

[taotaocui]

You can use PrimeTime to generate timing model for synthethis.
Just refer to PrimeTime's Document.

 

[tybhs]

Re: how to genetate timing and synthesis models of hard macr

Thank you ! IF I also want to generate synthesis models of a hard macro so that I can Integrate it into the top RTL module and sysnthesis the whole system, can you tell me how to do that, I mean, in what EDA tools? Thanks again!