Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to generate VCD file via VCS?

Status
Not open for further replies.
B

blaze1200

Newbie level 6
Joined
Nov 23, 2010
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Malaysia
Activity points
1,350
Hi,

My testbench is written in .cc format. What commands do i need to use in order to generate VCD file? (Via VCS) Thank you.
 

Re: Generate VCD file...

Never heard of .cc format!!

Is that Verilog or SV?
 
Re: Generate VCD file...

It is a C++ source file format.
 

i dont know abt .cc format but if your testbench is in .v format just add $vcdpluson; after you declare your initials and your vcd file will be generated after simulation.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top