How to generate transition fault in encounter test?

[dianin]

Hello Friends,

I'm new in Encounter Test(cadence tool for ATPG). I want to generate transition fault. I came to know that need to insert the OPCG (On Product Clock Generation) logic during synthesis for this.

Is any other way to generate the transition fault without inserting the OPCG, if yes please suggest me the steps , also want to know whether it is LOC or LOS mode.

Best Regards,
Dian

 

[maulin sheth]

If the clock is coming from top level ports thn OPCG is not required...
But if clock is coming through PLL thn it is required...

LOC and LOS mode is depends on us..whatever you want to choose you can choose...But LOC is more preferable..

 

[dianin]

Thanks Maulin!

Can you share the scripts/steps for transtiotion fault test. I'm running fixed-time test with giving clock frequency info. Is there anything I should give as a input besides pin-assignment file.

Thanks
Dian

 

[maulin sheth]

yea Sure.. I can share the scripts...
But I am using synopsys...I dont have any experience on Cadence Encounter...
So tell me if you want script for synosys..

 

[dianin]

Please send me the script for tmax, that will give me a idea to run it in cadence tool.

 

[maulin sheth]

The script is :
read_netlist -library $library_path
read_netlist $netlist
run_build $top_module_name
run_drc $spf_file
set_fault -model $fault_model_name
set_delay -launch $(LOC or LOS or LOES)
run_atpg
write_patterns.

But you get the command for encounter in the user guide...and also flow is given for transition fault model in the user guide..