How to generate the tming model about analog design?

[melonpy]

generate timing model

I want to generate timing model of analog design for STA timing analysis with digital design? Anyone know how?

 

[ayya]

I want to generate timing model of analog design for STA timing analysis with digital design? Anyone know how?

sorry ,i am a beginner in IC design
can you give me any explanation about "STA timing analysis" first?

 

[melonpy]

STA: Static Timing Analysis
For digital design timing analysis.
For mixed-signal design, we should simulation whole chip include digital and analog design, so I want to generate timing model of analog design.

 

[zyphor]

In my practice , you must do Spice simulation to get all data, and write the .lib file by yourself.

 

[philiphsu]

Using Simulator to get timing and function information.
then descript the analong block...
it's helpful for mixed-signal design...

 

[tlihu]

Set up testbench for the timing parameters you're interested in and run spice simulations against different corners. Then you can map the results into the best, typical, and worst timings models.