how to generate SDF at pre layout stage

[research235]

Hello every one

can any one tell me how can i generate a pre layout SDF file .. i tried by using like

create_clock_period.........
set_clock_latency.......
set_clock_trasition.........
write_timing –format sdf-v2.1 \
–output $design.sdf

i am alos using clock gating in my scripts, some one please let me the know correct method of generating the SDF file

thnks in advance

suresh

 

[yln2k2]

Hi ,

To Generate SDF you need RC network which is avaliable after layout .

One can do some estimation of prasitic at floor plan stage . But you need to read spef to generate SDF ?


Thanks & Regards
yln

 

[research235]

hello yln2k2

Thanks a lot for ur prompt reply ..

I am sorry if I am wrong but .. i read it as taht we can generate a SDF file just at synthesis level .. though this has no clock tree which is the major contributer of delay .. this can generated by using t he commnads of my prev message .,
please let me know if I am wrong

suresh

 

[yln2k2]

Hi Suresh,

Yes , I think you are correct . I heared people get SDF out of synthesis stage .
But that is not suitable for any timing simulations ? ( if you are planning to Gate Level simulations ) .



Thanks & Regards
yln

 

[Raptor]

SDF can be generated at pre-layout stage with the commands that you specified. very basic stuff but do keep clk and reset tree ideal.