how to generate bias voltage for big array circuits

[wateror]

bias voltage

I am designing a 64*64 pixel array driver circuits. Every pixel has a class ab amplifier in it. The question is how to design bias circuits for these amplifiers. It is better to mirror the current source at local area. But that will need 64*64 bias current source for the whole chip, which is impossible for layout. But if I just generate the bias voltage outside the pixel array, then collect it to all the bias circuirts inside the pixel. That may cause too much mismatch for the currents. So is there any better solution?

 

[tdy]

bias in array

it seems the bias current method has mismatch problem too.

 

[erikl]

back bias voltage

... 64*64 pixel array driver circuits ...
... generate the bias voltage outside the pixel array, then collect it to all the bias circuits inside the pixel. That may cause too much mismatch for the currents. ...

Buffer your bias voltage for low output impedance and route it to all pixels. Where you have to cross clock signals, take care to cross clk and clk_bar at adjacent positions (i.e. route clk & clk_bar (and any other digital phase/antiphase pairs, if they exist) in parallel). I've done this successfully for a 64*64 pixel array - 15 years ago.

 

[wateror]

Buffer your bias voltage for low output impedance and route it to all pixels. Where you have to cross clock signals, take care to cross clk and clk_bar at adjacent positions (i.e. route clk & clk_bar (and any other digital phase/antiphase pairs, if they exist) in parallel). I've done this successfully for a 64*64 pixel array - 15 years ago.

Use a buffer amplifier? But that will introduce more offset voltage for the buffer itself..
According to the monte carlo simulation, the mismatch will be around 20mv. That's too much. Now I chose the vdsat of bias Mos transistor to be 300mv since high vdsat will handle this much better. Is that ok?

I really have two clock signal( row_select & row_select_bar) crossing the bias voltage. But it should be ok as there is also a big parastic capacitor from bias voltage line to ground and the parastic cap from clock signal to bias voltage is only few fFs.

 

[erikl]

According to the monte carlo simulation, the mismatch will be around 20mv. That's too much.

I wouldn't think so. Other influences (process, voltage, temperature) will exhibit larger variations.

Now I chose the vdsat of bias Mos transistor to be 300mv since high vdsat will handle this much better. Is that ok?

Yes, that's fine.

I really have two clock signal( row_select & row_select_bar) crossing the bias voltage. But it should be ok as there is also a big parastic capacitor from bias voltage line to ground and the parastic cap from clock signal to bias voltage is only few fFs.

Few fFs per pixel?

 

[wateror]

yes, only few fFs per pixel. And since this is the row_select signal, it only switches only one time for one frame. Simulation shows that it won't cause too much variations on bias voltage. The most important thing is still the process and ground differences. I think that will cause at least 30mv mismatch.. Temperature should also be concerned. But I have no idea about the heat transfers. The total power consumption for my chip is 240mW. And the chip size is 7.5*7.5mm. Should I concern too much about the heat transfer of my package?

 

[erikl]

yes, only few fFs per pixel.

Makes 4*few pFs in total. Quite a lot!

Simulation shows that it won't cause too much variations on bias voltage.

Ok, that's the important thing.

The total power consumption for my chip is 240mW. And the chip size is 7.5*7.5mm. Should I concern too much about the heat transfer of my package?

\[4 mW/mm^2\] isn't much for silicon. And the power dissipation's distribution is rather uniform, I guess. So your concern is just the temperature increase over the max. ambient temperature. With a typical - say - 80 K/W thermal resistance of your package, you'll get a temperature rise of ≈20 K on top of your max. ambient operating temperature, which you should consider in simulation.

 

[dick_freebird]

Perhaps you want to break up the distribution along
lines of any hierarchy you may have (e.g. a current
source rack per row each with its own master), and
the main reference with either 64 current branches or
make a voltage mode, replica-feedback driver and
make the row racks look like 64-output transconductors.

 

[wateror]

Perhaps you want to break up the distribution along
lines of any hierarchy you may have (e.g. a current
source rack per row each with its own master), and
the main reference with either 64 current branches or
make a voltage mode, replica-feedback driver and
make the row racks look like 64-output transconductors.

Yeah, I plan to make one refence for each column.
And because the coupled digital signal (row_sel & row_sel_bar) is differential, the bias voltage should be concerned as a invariant signal.
And the ground of the bias circuits is far from digital circuits. So there shouldn't be too much noise.