How to generate a variable capacitor in cadence?(update)

[Davidy]

I want to generate a variable capacitor in cadence such as the Cs in figure below.
Cs is changing its capacitive value in a frequncy of 1kHz.
I try making a Cs using VerilogA language. But this can only generate varible current.
I really wonder how to generate a real varable capacitor, which is changing its value with time.

Now I find a paper about generate a varable capacitor in Pspice with Voltage-control current source and other dependent sources.
But I don't know how to implement it in Cadence for spectre simulation. I have tried once but the Voltage-control current source can not be used in the way as the paper "variable capacitor" I upload.

 

[Hughes]

How to generate a variable capacitor in cadence?

"I(t) = C * V(t)" is neither correct in syntax nor correct in agorithm. It should be:
I(PLUS, MINUS) <+ C * ddt(V(PLUS, MINUS))

 

[sengyee88]

Re: How to generate a variable capacitor in cadence?

Alternatively, you can use ideal ADC from the model writer, and construct a weighted capacitor bank. Using the digital bits to control the weighted capacitor, hence obtaining a discrete varactor. You can always increase the ideal ADC resolution, to approximate a continuous time varactor.

 

[Davidy]

Re: How to generate a variable capacitor in cadence?

Thank for Hughes's and sengyee88's help.

But except that measure can I implement variable cap. in other easy way?

 

[sengyee88]

Re: How to generate a variable capacitor in cadence?

Writting veriloga perhaps is the easiest, provided you knows veriloga.

However, i still prefer the ideal ADC and weighted cap approach, as the weighted cap can be substituted by real cap model that given from the PDK. You can see the full effect over PVT variations.

 

[Hughes]

Re: How to generate a variable capacitor in cadence?

Thank for Hughes's and sengyee88's help.

But except that measure can I implement variable cap. in other easy way?

hspice supports voltage-controlled capacitors. But for spectre, you need veriloga.

 

[teteamigo]

Variable capacitor based in one capacitor can be made with a DAC putting gain between capacitor nodes (Voltage Controlled Source Voltage).

 

[ahmad_abdulghany]

Re: How to generate a variable capacitor in cadence?

Alternatively, you can use ideal ADC from the model writer, and construct a weighted capacitor bank. Using the digital bits to control the weighted capacitor, hence obtaining a discrete varactor. You can always increase the ideal ADC resolution, to approximate a continuous time varactor.

What is Model Writer??
How to use it?
Thanks,

 

[teteamigo]

Variable capacitor based in one capacitor can be made with a DAC putting gain between capacitor nodes (Voltage Controlled Source Voltage).

**broken link removed**