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How to generate a psuedoe random sequence?

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boeysue

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Is there any document for that topics or can anyone express that for me?

Thanks for answering..
 

samcheetah

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what do you want to know about it???? be a little more specific. do you want Verilog or VHDL codes or do you want an implementation with a microcontroller like PIC.

a simple search on edaboard and google will give you alot of info
 

sarath51

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What do u want to implement a psuedo random sequence generator in RTL ( u can find a example of that HDL chip design - smith book) or a random sequnce for RTL verification
 

eternal_nan

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Search for Linear Feedback Shift Register (or LFSR)on google. This structure is basically a circular shift register with XOR gates between some of the stages, it produces a pseudo-random sequence when clocked...
 

pimr

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hi,
you can go through a chapter on random number generation in a book by populis "Probability, Random Variables, and Stochastic Processes".You can find c code for random number generation in "numerical recipes in c" it is available online.If u r interested in mcu implementation of it check this application note by ti
https://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=swra041
it is concerned with frequency hopping but you can also find code for random number generation.
pimr
 

boeysue

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I want a psuedoe random sequence generate to add to my answer in order to spread the error.
It may be used in digital signal processor or asic...
Thanks for the above discussion I will check in the "numerical recipies in C".
 

jitendra

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Hi,
You can use LFSR. Refer following link for some discussion on LFSR.

**broken link removed**

Regards,
Jitendra
 

DrDolittle

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Pseudo random number generation is given in Numerical recipes in C. Also using Box Mueller method it can generated

Regards
drdolittle :)
 

shakalaka

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you can use LFSR (Linear Feedback Shift register) method....it most reliable and have capability to generate any kind of patterns.....


you may also want to learn about CRC (Cyclic Redundancy check)...this will help you solve...how you can make use of LFSR.....for detecting the errors...
 

FLEXcertifydll

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Yes it is the LFSR, which is the step and length of the module.
 

omid219

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I have some verilog files that implement different kinds of lfsr. Pleas email me, I can send them to you.
 

corgan

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Most of lfsr approach can't generate psuedo random sequence with
zero number.
Doesn anyone know how to generate psuedo random sequence with zero number?
 

deh_fuhrer

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linear feedback shift register is the best thing for that..there is lot of material available in edaboard.com.
(LFSR is used in BIST also)..

Added after 1 minutes:

see this:
 

cmaulik26

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Re: How to generate a psuedoe random sequence in vhdl coding ??

i need vhdl coding for pusedo random sequence generator. Pls help me !:roll:

- - - Updated - - -

i also need in vhdl code. Pls sent it
..
 

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