In the old days of predicting BER with margin testing for high speed clock and data separators, we used many different tools to measure window margin.
But often one of the most useful tools was to inject random jitter into the system to reduce phase margin but still be error free with minimal margin to see if any environmental stress would produce an error.
The method used to inject error was digital and it was applied to the data rather than the clock, because it was used for MFM protocol, so data was stored in the data edges phase timing.
Each incoming analog data converted to digital produced a clock edge that was used to advanced a PRSG random multiplexer which then selected one of 3 taps on a digital delay line for the data pulse to be multiplexed, that would represent Early, Normal and late. Perhaps you can consider this method for your clock.
The offset was predetermined at 20 % of the ideal window margin, but could be anything so rather than random jitter, it was fixed jitter but with random phase early/ normal/ late.
It was very useful for predicting loss of margin in soft and hard error rate when other stress was applied as a GO/NO GO test.