Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to generate a clock signal with random noise in Cadence Spectre?

Status
Not open for further replies.

BackerShu

Member level 3
Joined
Dec 22, 2007
Messages
57
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
USA
Activity points
1,795
I am trying to generate a clock signal with random noise, but not using complicated VCO models in Cadence Spectre.

One possible way I think is to use the vsource in analogLib with "prbs" type, and specify the bit file with "...0101..." pattern. So that, I can put the noise for the pattern as provided by the vsource model.

But I don't know how to construct the bit file. Could someone please explain how to do it by brief steps or direct me to some reference?

Or any other simple way to generate such clock with random noise?

Thank you!
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,707
Helped
4,340
Reputation
8,689
Reaction score
4,303
Trophy points
1,393
Activity points
130,467
Hi,

There is not much information. No frequency, no information about spread spe trum.

Maybe a NCO with added random numbers is a solution.

Klaus
 

BackerShu

Member level 3
Joined
Dec 22, 2007
Messages
57
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
USA
Activity points
1,795
Hi,

There is not much information. No frequency, no information about spread spe trum.

Maybe a NCO with added random numbers is a solution.

Klaus

Thank you Klaus,

I think NCO definitely will do that.

My intention is not to design such a clock source. I just need some clock with configurable random noise for simulation of some circuit which requires such a clock source. That's why I wanted to keep it simple. The vsource in "prbs" type is the simplest way I know.

If there is something already exists in Spectre, that will be even better.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,281
Helped
2,126
Reputation
4,257
Reaction score
1,983
Trophy points
1,393
Location
USA
Activity points
58,399
What I do is, stack the primary source (with finite edge rate,
or even a sine) plus several off-frequency, low amplitude sine
sources to add some "chaos" and then square it up with either
a limiting controlled source, or just an inverter chain. The chaos
will give you edge jitter which I imagine is what you're after?
The edge rate of the primary source determines the voltage
to jitter-time transform.
 

SunnySkyguy

Advanced Member level 5
Joined
Sep 26, 2007
Messages
6,743
Helped
1,675
Reputation
3,348
Reaction score
1,644
Trophy points
1,413
Location
Richmond Hill, ON, Canada
Activity points
50,733
In the old days of predicting BER with margin testing for high speed clock and data separators, we used many different tools to measure window margin.

But often one of the most useful tools was to inject random jitter into the system to reduce phase margin but still be error free with minimal margin to see if any environmental stress would produce an error.

The method used to inject error was digital and it was applied to the data rather than the clock, because it was used for MFM protocol, so data was stored in the data edges phase timing.

Each incoming analog data converted to digital produced a clock edge that was used to advanced a PRSG random multiplexer which then selected one of 3 taps on a digital delay line for the data pulse to be multiplexed, that would represent Early, Normal and late. Perhaps you can consider this method for your clock.

The offset was predetermined at 20 % of the ideal window margin, but could be anything so rather than random jitter, it was fixed jitter but with random phase early/ normal/ late.

It was very useful for predicting loss of margin in soft and hard error rate when other stress was applied as a GO/NO GO test.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top