How to generate a clock signal with random noise in Cadence Spectre?

[BackerShu]

I am trying to generate a clock signal with random noise, but not using complicated VCO models in Cadence Spectre.

One possible way I think is to use the vsource in analogLib with "prbs" type, and specify the bit file with "...0101..." pattern. So that, I can put the noise for the pattern as provided by the vsource model.

But I don't know how to construct the bit file. Could someone please explain how to do it by brief steps or direct me to some reference?

Or any other simple way to generate such clock with random noise?

Thank you!

 

[KlausST]

Hi,

There is not much information. No frequency, no information about spread spe trum.

Maybe a NCO with added random numbers is a solution.

Klaus

 

[BackerShu]

Hi,

There is not much information. No frequency, no information about spread spe trum.

Maybe a NCO with added random numbers is a solution.

Klaus

Thank you Klaus,

I think NCO definitely will do that.

My intention is not to design such a clock source. I just need some clock with configurable random noise for simulation of some circuit which requires such a clock source. That's why I wanted to keep it simple. The vsource in "prbs" type is the simplest way I know.

If there is something already exists in Spectre, that will be even better.

 

[dick_freebird]

What I do is, stack the primary source (with finite edge rate,
or even a sine) plus several off-frequency, low amplitude sine
sources to add some "chaos" and then square it up with either
a limiting controlled source, or just an inverter chain. The chaos
will give you edge jitter which I imagine is what you're after?
The edge rate of the primary source determines the voltage
to jitter-time transform.

 

[D.A.(Tony)Stewart]

In the old days of predicting BER with margin testing for high speed clock and data separators, we used many different tools to measure window margin.

But often one of the most useful tools was to inject random jitter into the system to reduce phase margin but still be error free with minimal margin to see if any environmental stress would produce an error.

The method used to inject error was digital and it was applied to the data rather than the clock, because it was used for MFM protocol, so data was stored in the data edges phase timing.

Each incoming analog data converted to digital produced a clock edge that was used to advanced a PRSG random multiplexer which then selected one of 3 taps on a digital delay line for the data pulse to be multiplexed, that would represent Early, Normal and late. Perhaps you can consider this method for your clock.

The offset was predetermined at 20 % of the ideal window margin, but could be anything so rather than random jitter, it was fixed jitter but with random phase early/ normal/ late.

It was very useful for predicting loss of margin in soft and hard error rate when other stress was applied as a GO/NO GO test.