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how to fix problems when fails to post simulation

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owen_li

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I verified my design in RTL using VCS. And its function is ok. After I synthesized my design, it failed in netlist simulation. Now, what should I check and how? Thank you!
 

no_mad

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Hi,

U need to check your RTL code.
Maybe u have used non-synthesizable code such as initial or time delay or incomplete sensitivity list or etc.

U can get more info from any verilog book.

My personal advice when writing RTL code.
Always think hardware and think synchronous design.

Hope it helps.
 

vlsi_freak

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Hi

If the post simulation does not work, still u can have a try by downloading to FPGA. Check whether its working or not. Before downloading, make sure that all your timings are met.

Have a try..and all the best.

Thanks
 

au_sun

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Check your Design timing, first check whether ur netlist passes Timing Analysis check in the Synthesis tool.

Ur design functionality may fail due to timing violation in ur design after synthesis.........

check for it.
 

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