How to express this equation using "assign" in verilog

[nbuzs]

Any suggestion on the expression using verilog will be thankful.


Input Data is D[3:0], encoded output Z[6:0]

Z = (D mod 15) + (8-1)*(2ⁿ-1)

listed in below table

D[3:0] n Z[6:0]
---------------------
0 0 0
1 1 8
2 1 9
3 2 24
4 2 25
5 2 26
6 2 27
7 3 58
8 3 57
9 3 58
10 3 59
11 3 60
12 3 61
13 3 62
14 3 63
15 0 0

 

[kornukhin]

You can use hard coding:
assign Z =
D==4'h0 & n=2'h0 ? 6'h0 :
D==4'h1 & n=2'h1 ? 6'h8 :
...
Synthesis tool will optimize this logic.

Another way:
assign Z = D + 7*(1<<n - 1);

 

[nbuzs]

thanks for kornukhin reply.

I'm try to writing in this way
___________________________________________________________________________
wire [3:0] incd3;
wire [3:0] exp3;

assign incd3 = D + 1;
assign exp3 = {incd3[3], ~incd3[3] & incd3[2], ~incd3[3] & ~incd3[2] & incd3[1], 1'b0};

assign Z = (D % 15) + (8-1)* (exp3 - |exp3);
____________________________________________________________________________