Can you post the circuit and the bode-plot open-loop?
Right now I can only give you common problems that designers meet that lead to oscillation:
1) Forget to analyze both common-mode oscillation AND differential-mode oscillation
2) Realistic parasitics around Vcc and GND, as well as output are not included.
3) When doing loop analysis, do not properly open the loop to find gain/phase margin.
4) Look at just PM and GM, and do not look at the shape which may indicate problems elsewhere.
5) Do not consider all possible load impedances. Just because it's stable at your simulated load does not mean it will be stable at all loads.
Hope this helps for now. Again, if you post the circuit, frequency of oscillation and how you simulated phase/gain margin (and their plots) then we can provide you with a lot more feedback.
Greg