hi,all
How to dump all signals' waveform when import VHDL into verilog testbench,
when top level testbench is verilog code(other are VHDL code) , use
initial
begin
$dumpfile ("debussy.vcd");
$dumpvars (0,top);
#20000
$finish;
end
in top level dump waveform, many vhdl signal such as control signal can not been catched? How to dump all the signals?
Thanks a lot!!!
Depends on your simulator actually. The problem is VCS is not defined for VHDL in VHDL LRM, tools have extended that support though. I know in VCS adding $vcdpluson will dump Verilog + VHDL. They also have command line (ULCI) to do the same. NC & MTI also have similar TCL commands.
hi,all
How to dump all signals' waveform when import VHDL into verilog testbench,
when top level testbench is verilog code(other are VHDL code) , use
initial
begin
$dumpfile ("debussy.vcd");
$dumpvars (0,top);
#20000
$finish;
end
in top level dump waveform, many vhdl signal such as control signal can not been catched? How to dump all the signals?
Thanks a lot!!!