how to dump all signal waveform when import VHDL int Verilog

[hgz]

verilog dump signals

hi,all
How to dump all signals' waveform when import VHDL into verilog testbench,
when top level testbench is verilog code(other are VHDL code) , use
initial
begin
$dumpfile ("debussy.vcd");
$dumpvars (0,top);
#20000
$finish;
end
in top level dump waveform, many vhdl signal such as control signal can not been catched? How to dump all the signals?
Thanks a lot!!!

 

[aji_vlsi]

vcs dumpvars fsdb

Depends on your simulator actually. The problem is VCS is not defined for VHDL in VHDL LRM, tools have extended that support though. I know in VCS adding $vcdpluson will dump Verilog + VHDL. They also have command line (ULCI) to do the same. NC & MTI also have similar TCL commands.

Which simulator are you using?

HTH
Aji
http://www.noveldv.com

hi,all
How to dump all signals' waveform when import VHDL into verilog testbench,
when top level testbench is verilog code(other are VHDL code) , use
initial
begin
$dumpfile ("debussy.vcd");
$dumpvars (0,top);
#20000
$finish;
end
in top level dump waveform, many vhdl signal such as control signal can not been catched? How to dump all the signals?
Thanks a lot!!!

 

[Ansunamu]

fsdb vhdl

I think maybe you can consider to dump FSDB file . It's better than VCD

 

[hgz]

dumping probes with tcl in vcs

I use ncsim simulate. thanks.

 

[roger]

vcdpluson in vhdl

I use ncsim simulate. thanks.

avoid using variables in your VHDL design.
VCD file seemed cannot record them

 

[amaccormack]

dump, verilog

Read up on the simulator's probe command. I think the syntax is something like:

probe -all -depth all -variable :SCOPE

to include all VHDL signals