hi
Your switching diagramm similar to SPI(Serial Peripheral Interface) switching diagramm, try to find some information about SPI, also you can easily google some vhdl examples.
actually the data is available with me is parallel data of 20 bit that i have to convert to serial with shift register but shifter register will take one clock cycle to load tha data before shifting but in the diagram before the strobe is low there is no clock cycle available to load the load now how do i do this.
You have 20 bit shift register, it's MSB bit is an output, Strobe is a Clock Enable of the register. After first clock MSB-1 is an output and so on. You have to load next 20 bit value to shift register before next strobe comes.
i guess that it is your university hometask, if to follow these time requirements your max frequency will be 50 KHz, you need external oscillator with such frequency, because internal resources can not produce such low period clock. It is not so trivial task to create some delays in real FPGA. So I guess that your task is to create a model, not a synthesizable design, use such vhdl statements as "after 50 us".